Receiver circuits, like serializer/deserializer (SERDES) circuits, are becoming ubiquitous in many computational environments. The SERDES can compress a relatively wide, parallel input into a relatively narrow, serial signal (e.g., a single “bit,” differential signal) for communication over a serial bus. The serial bus switches at an appreciably higher rate than the parallel bus, and serial communication of the data stream tends to reduce cost, complexity, power, and board real estate relative to comparable parallel communications. As bus speeds increase, parallel communications manifest even higher power consumption and more issues relating to timing (e.g., skew mismatches and bit misalignment), making SERDES circuits even more attractive.
Often, the receiver circuit includes an analog-to-digital converter (ADC) circuit that attempts to converts a received analog serial signal into discrete bits. This can involve determining where bit transitions occur and what bit value to record, often in context of noisy data, small signal levels, and other difficult conditions. The ADC can be configured as a data slicer for generating data sampler decisions. The ADC can also include, or can be in communication with, error slicers for clock data recovery (CDR) and decision feedback equalization (DFE) adaptation. For various reasons, effective clock path mismatches can occur between the data slicers and error slicers, which can further frustrate accurate determination of serial bits from the analog signal.